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datasheet GSC3E/lpx and gsc3f/lpx high performance, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com sirfstariii architecture p roduct d escription the GSC3E/lpx and gsc3f/lpx are the pin-for-pin compatible, lowest power versions of the advanced GSC3E(f)/lp receiver in a single package. the baseband has been ported to 65 nm technology, enabling an additional power reduction of up to 30 percent. in the GSC3E/lpx, the baseband and rf are integrated into the 7 mm x 10 mm x 1.4 mm package. in the gsc3f/lpx, flash memory is included in the package making for an extremely compact design. th e GSC3E(f)/lpx includes a powerful gps dsp integrated with an arm7tdmi micro- processor and 1 mb of sram. the GSC3E(f)/lpx archi- tecture uses an fft and matched filter that delivers performance equivalent to more than 200,000 corre- lators. this represents a quantum leap forward in gps performance. a rchitecture h ighlights next generation, lowest power, gps performance x 200,000+ effective correlators for fast ttff and high sensitivity acquisitions x supports 20-channel gps x high sensitivity for indoor fixes x extremely fast ttffs at low signal levels x real-time navigation for location-based services x low 100 ms interrupt load on microprocessor for easy ip implementation x sbas (waas, msas, and egnos) support sirfloc tm client agps support x sirf patented end-to-end solution x multimodes: mobile cent ric to network centric x mutli-standard support: 3gpp, 3gpp2, pdc, iden, and tia-916 x supports ai3 and f interfaces gsw3?modular software support x api compatible with gsw2 x rtos friendly p roduct h ighlights gsc3f/lpx?digital, rf, and flash single chip x digital, rf, and 4 mb flash in a single package x small 7 mm x 10 mm x 1.4 mm, bga package x arm7tdmi cpu and sram to enable user tasks x accepts six reference frequencies between 13 mhz and 26 mhz x extensive gps peripherals: 2 uarts, battery-backed sram, and 14 gpios lowest power x under 60 mw at full power x 46 mw tracking power x push-to-fix ? reduces power as much as 98% built on proven experience x ip integration experience x highly developed design tools x fcc e911 compliance experience figure 1. sample architecture diagram (optional) eclk GSC3E/lpx and gsc3f/lpx reset serial data 1 pps serial data power battery rtcxtal reference clock gps antenna lna rf filter www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 2 s i rf star iii a rchitecture d escription sirfstar iii architecture has the performance required to meet the toughest challenges. sirfstar iii products can acquire in only seconds even at low signal levels, and can track signal levels as low as -159 dbm. sirfstar iii architecture supports real-time navigation in urban canyons as well as high sensitivity acquisition needed for attenuated and weak signals. GSC3E/lpx and gsc3f/lpx d escription the GSC3E(f)/lpx rf section is the most highly integrated lowest-power sirf rf silicon to date. the rf section integrates an rtc as well as many compo- nents that were previously on the board into the silicon while reducing rf die curr ent consumption to 13 ma. while some a-gps receiver s can experience lengthy acquisition times at low signal levels, sirfstar iii archi- tecture enables unmatched ttff at extremely low signal levels. this allows a much richer user experience, which is import ant because slow or poorly performing applications ofte n fail in the market place. the GSC3E(f)/lpx can share an rtc and the reference clock is supported by different input frequencies. this means that designs can be simpler and smaller, and batteries can be smaller and last longer. the small form factor of the GSC3E(f)/lpx in combi- nation with the frequency sharing abilities of the rf section allows for very compact receiver designs. the sensitivity of the GSC3E(f)/lpx can also be used to help overcome non-optimal antennas such as those that are often used in consumer designs. f unctional d escription the GSC3E(f)/lpx is optimize d for location applications requiring high performance with low power in a small form factor. the GSC3E(f)/lpx contains a powerful gps engine built on a low powe r 65 nm cmos process with a 1.2 v core. the GSC3E(f)/lpx can run using only 2.85 v power utilizing internal voltage regulators in the digital section. these regulators can be bypassed for lower power consumption if 1.2 v power is available. the internal functions of the digital section are split into two main parts that are defined by the buses that run them. the arm system bus (asb) has all the core cpu components and the sirf ip bus (sipb) contains all the gps and other dsp peripherals. the arm and dsp share memory for a more cost effective and gate efficient design. the digital section is described first followed by the rf section. information map digital section description. . . . . . . . . . page 3 rf section description . . . . . . . . . . . page 6 electrical and power section . . . . . . . . page 14 mechanical section . . . . . . . . . . . . . page 24 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 3 figure 2. GSC3E(f)/lpx internal block diagram digital section description s i rf star iii c ore the sirfstar iii core is built around a reconfigurable high-output segmented matched filter in conjunction with an fft processor, which can simultaneously search all 1023 chips of the gps code over a wide frequency range for fast in itial acquisition with large uncertainties. the flexibility of the core allows the core processing engine and memo ry to be reconfigured to track more than 20 channels using the same hardware. this flexibility makes the sirfstar iii a highly efficient engine for a wide variety of location applications. the sirfstar iii core contains a built-in sequencer, which handles all the high-rate in terrupts for gps and sbas (waas, msas, egnos) tracking and acquisitions. after initialization, the core autonomously handles all time critical and low latency acquisition, tracking and reacquisition tasks of gps and sbas. the core provides interrupts, which in turn pr ovides measurement data to the cpu for computation of the navigation solution. the sirfstar iii core also provides time and frequency management. this includes the basic clock counters, alarms, edge-aligned ratio counters (earc) and synchronization blocks used to provide the system time line and to transfer accurate time and frequency into and out of the system. an earc is an improved (sirf patented) type of ratio counter used for enhanced frequency accuracy among alternate clocks. arm7tdmi the arm7tdmi is an ideal core providing high perfor- mance and low power consumption. the arm7tdmi cpu can run at speeds up to 50 mhz and is supported rfa rtc osc tcxo buffer internal loop fltr n/r pll synthesizer mixer agc a / d if filter vco sirf bridge arm7tdmi cache boot rom sram ram sharing dsp ram bus interface sirfstar iii core watchdog timer gpio spi duart rf section digital section clock module interrupt controller 4mb flash battery backed sram mux www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 4 by a wide variety of development tools. because the sirfstar iii core eliminates the need for the cpu to service high-rate interrupts, it is easier than ever to use the arm processing power for user tasks. the arm7tdmi includes a jtag interface, which provides a standard develo pment / debugging interface that connects to a variety of off-the-shelf emulators. this provides single-step, trap and access to all the internal registers of the digital section of the GSC3E(f)/lpx. k eep -a live (ka) s ection this group of functions is maintained by a continuous voltage supply from a backup battery. ka comprises the rtc oscilla tor (see rf section), rtc counter and comparators (rtc), battery backed sram (bb-sram) and finite state machine (fsm). proper power sequencing mu st be followed to ensure that ka operation is not disr upted by external voltage or current leakage. refer to figure 8, ?power sequencing diagram,? on page 19. battery-backed sram (bb-sram) the GSC3E(f)/lpx contains a small block of battery- backed sram, which contains all necessary gps infor- mation for hot starts and a small amount for user configuration variables. bb -sram retains critical data from previous operation to enable shorter ttffs under all startup conditions rtc counter and comparators the very low-power logic se ction provides timing for operation of fsm and for self-managed power saving modes such as adaptive trickle power (atp), advanced power management (apm), and push-to-fix (ptf). the rtc is critical for operation of hot and warm starts. a large master counter avoids all time ambiguity. comparators trigger ?wake-up? events while in hibernate and are used as event timers during normal operation. the rtc cloc k frequency is calibrated during operation for optimum hot- and warm-start ttffs. power control finite state machine the fsm controls power sequencing for all operating modes, including full power mode, and requires a stable rtc clock input. inputs to the fsm come from external nsreset and on_off signals and internal rtc events. nsreset assertion is allowed and requ ired only when ka section supply voltage is first applied. all other control of power sequences is initiated only by pulses to on_off input, and by serial messages for ?soft-off? and power- management configuration. fsm output controls all internal resets and external control lines nreset (for jtrst and if needed for external flash memory), nwakeup (for control of baseband section voltage supply), rfpwrup (for control of rf section voltage supply). nwakeup and rfpwrup outputs are required to control proper sequencing of external voltage supplies to rf and baseband in all modes an d they enable autonomous self-managed power modes such as atp, apm, and ptf. b oot rom the boot rom contains a small code set that can load a set of user code through uart port a into the sram, and execute it. this allows the GSC3E(f)/lpx, for example, to update flash. b us i nterface u nit the bus interface unit (biu) provides an external 16- bit interface for memory or peripherals supporting half- word transactions. each chip select addresses a 2- mbyte address space with an independent start address. the external source for boot code memory must be selected by cs0 . the number of wait states for each chip select can be independently set up to a maximum of seven. c ache a two-way 8 kb associative instruction/data cache provides a fast access memory for cs0 only. GSC3E/lpx will cache only the first 512 kb of external flash memory on cso while addressing a maximum of 1mb (8mbits) of external flash memory. www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 5 c lock m odule this module generates all in ternal clocks such as the signal processing (sp) clock and bus (b) clock from the acquisition clock. the acquisition clock is generated by the rf section. the clocks generated by clock module run the sirfstar iii dsp and arm and control the various power management modes allowing for maximum power savings and system flexibility. duart the GSC3E(f)/lpx contains two full duplex serial ports. one port is normally used for gps data and receiver control and the second serial port can be used as an alternate communication channel. the transmit and receive side of each port contains a 16-byte deep fifo with selectable bit rates ranging from 1.2 to 115.2 kbaud. with special flashing software, maximum baud rate of 921.6 kbps is available. gpio u nit the GSC3E(f)/lpx supports a variety of peripherals through 14 gpio lines. the gpio unit centralizes management of all gpio lines and provides a simple software interface for their control. flash the gsc3f/lpx integrates 4 mbits of flash memory. this eliminates the need for external flash and signifi- cantly simplifies the routing associated with integrating a gps receiver into a board design. this chip is not available in a pre-flashed version. i nterrupt c ontroller the interrupt controller manages all internal or external sources of interrupts. these include the sirfstar iii core, sbas, dsp, duart and external user interrupts. s i rf b ridge u nit the sirf bridge units (sbu1 and sbu2) provide low power access to peripherals. sbu1 provides access to general purpose arm peripherals such as the serial port uarts, rtc, and interrupt controller. sbu2 provides access to the dsp core and its associated memory. the dsp core also uses this bus for internal communications. the arm is able to perform byte, half-word, and word transactions via the 32-bit peripheral busses. sram the on-chip sram size is 1 mbit (32k x 32) memory that can be used for instructions or data. in many applications it eliminates the need for external data memory. the sram is designed for a combination of low power and high speed, and can support single cycle reads for all bus speeds. s erial p eripheral i nterface the serial peripheral interface (spi) port handles communication, such as reference frequency selection, agc, and power control, between the digital and rf sections. the rf section acts in slave mode and can only be controlled by the digital section using sirf software. the spi port consists of spi_clk, spi_di, spi_do, and spi_ceb for the rf section, and corre- sponds to sk, si, so, and ceb in the digital section. the spi port does not support additional spi devices. it is only used for internal communication between rf and bb. dsp ram and ram s haring the GSC3E(f)/lp includes shared ram which is allocated between arm and dsp core. this keeps the overall size of the chip down while maximizing the availability of memory. f actory t esting the GSC3E(f)/lpx uses a memory built-in self-test called membist to provide co mplete coverage of all the memory during chip test ing and qualification. this is combined with the scan test logic using automatic test pattern generation (atpg) at the wafer level to provide functional test coverage. (these functions are not available to customers.) www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 6 rf section description rf a mplifier (rfa) the rf section receives the gps l1 signal via an external antenna and external lna. the l1 input signal is a direct sequence spread spectrum (dsss) signal at 1575.42 mhz with a 1.023 mbps bi-phase shift keying (bpsk) modulated code. because the input signal power at the antenna is nominally -130 dbm (spread over 2 mhz), the desired signal is below the thermal noise floor. with a front-end input compression point of -65 dbm, rejection of large out-of-band signals is possible given filtering in the if section. the rfa uses a single-ended rf input for ease of use. sirf run- time firmware provides support for customer production testing of key parameters. i mage -r eject m ixer the image-reject mixer is a double balanced design, which significantly reduces common mode interference. the image reject mixer block also contains an i-q phase shift combiner. this circuit properly phase shifts and sums the i and q outputs internal to the image reject mixer to a single channel and achieves an rf image suppression in excess of 20 db. by using an image reject mixer, an inex pensive pre-select rf filter may be used. the mixer and on-chip 1571.424 mhz vco produce an if center frequency of 3.996 mhz. if f ilter an if filter is implemented between the mixer and agc amplifier to provide an anti-aliasing function before a/d conversion. in the rf section, the if filter has been integrated on-chip, thus minimizing the number of external parts on the board. this filter typically provides >20 db roll-off at the alia s frequency (located at f s - f if , where f s is the adc sample rate), which makes the contribution of c/n 0 degradation due to nyquist noise folding insignificant. thus, the combined effects of if noise aliasing and rf image conversion have a negligible impact to c/n 0 performance. agc a mplifier and c ontrol b lock the agc amplifier provides the additional gain needed to optimally load the signal range of the 2-bit a/d converter. the agc if gain is digitally controlled by an agc control block, which loads and registers digital gain setting words from gsc3 e(f)/lpx via the four wire spi interface. the 5-bit agc control register allows the sirfstar iii receiver to compensate for roughly 50 db variation in system gain for all causes including temper- ature front-end configuration and process variations. a/d c onverter the agc amplifier output drives a 2-bit a/d converter, which provides sign and magnitude output bits to the interface block. the combination of 2-bit quantization and oversampling in the sirfstar iii architecture provides significant improvement in c/n 0 and cw jamming immunity over 1-bit systems. rtc o scillator this circuit is designed to drive a 32.768 khz crystal. this oscillator is always operational, including during the sleep cycle of the rf section. the main section is specifically designed using a pseudo-inverter topology that provides sufficient gain to start oscillation of the crystal with minimum startup time and minimum current consumption. the crystal is connected between the input and output of this inverter. an internal differ- ential stage followed by a series of inverters is included to convert and drive the oscillation amplitude to cmos levels. the rtc oscillator circuit also includes start-up circuitry for the bias section to guarantee fast and reliable startup. r eference f requency s ource the reference clock circuit is designed to be driven by a 13 to 26 mhz tcxo (0.5 ppm temperature coeffi- cient). f requency s ynthesizer the rf section gps down-converter includes an n/r synthesizer that allows the use of a range of reference tcxos. the synthesizer generates the local oscillator signal for the image reject mixer and also generates the clkacq. if the reference clock is selected at 16.369 mhz, the clkacq can also be generated from the reference crystal directly (this is the default). www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 7 the synthesizer is programmed by software using ?n? and ?r? words. ?n? represents the division ratio of the loop and ?r? represents division ratio of the reference signal. [f out / f ref ] = n / r n and r inputs are determined by the baseband controller using configuration straps at start-up. the frequencies supported are shown below. the local oscillator and sa mple clock (clkacq) are derived from an on-chip pll synthesizer block. the vco, dividers, and phase detector are provided in the chip. use of 16.369 and 24.5535 mhz offers optimal receiver sensitivity. i nternal l oop f ilter an internal loop filter is implemented in rf section to reduce pin count and to impr ove noise immunity on the control node of the vco. the internal loop filter is automatically adjusted for each input reference frequency to optimize the poles and zeros to achieve optimum loop stability. the loop filter of the rf section synthesizer is an on-chip rc filter. c lock _m ux if the system clock is 16.369 mhz, the clock mux circuitry allows additional power saving modes by switching off the pll and using the tcxo reference as the source of the system clock. the selection of the clock is programmed by the digital section through the spi interface and external boot strap resistors. f ref mhz 13 16.369 16.8 19.2 24.5535 26 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 8 figure 3. 7989 series C 16.369 mhz configuration ss[0] spi_ceb so spi_di sk spi_clk si spi_do sign_mag_o sign_mag_i clkacq_o clkacq_n jtdi jtms jtck eclk sreset vdd_bb cpu supervisor GSC3E/lpx gnd_bb vdd d3 d0 re flash boot d7 d2 d1 wakeup on-o txa cmos level rxa vddpll_o vddk gnd_bb tmode pll_filter vcc_rtc / vdd_rtc vdd_reg_in vdd_flash vcc_rf 32.768 khz osc xtalin vdd_bb v rtc_xo rtc_xi to rf reg circuits reset grfrst jtrst rfpwrup unswitched unswitched v rin rtc_out cs[1] / tsync cs[1] and eclk are slc interface signals (opt) ed[15:0] main control for start-up and power-down vdd-bb to vdd-bb reg circuits jtdo } moe cs[0] flash ea[19,0] mwe ed[15,0] rf filter rfa rfin (2) (2) (2) vcc_io_ext nc (1) * 1 nf capacitor was recommended in previous designs, but use of this capacitor is now optional. * notes: (1) vcc-io-ext is a no-connect pi n. internal power connections are made and no inte rnal wirebonds connect to pb. this is to enh ance the chip esd performance. (2) denotes a very small, short low c test point is desirable. s ample c onfiguration c onnection d iagram f or gsc3 e /lp x www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 9 figure 4. 7985 series C 16.369 mhz configuration ss[0] spi_ceb so spi_di sk spi_clk si spi_do sign_mag_o sign_mag_i clkacq_o clkacq_n jtdi jtms jtck eclk sreset vdd_bb cpu supervisor gsc3f/lpx gnd_bb vdd d3 d0 re flash boot d7 d2 d1 wakeup on-o txa cmos level rxa vddpll_o vddk gnd_bb tmode pll_filter vcc_rtc / vdd_rtc vdd_reg_in vdd_flash vcc_rf 32.768 khz osc xtalin vdd_bb v rtc_xo rtc_xi to rf reg circuits reset grfrst jtrst rfpwrup unswitched unswitched v rin rtc_out cs[1] / tsync cs[1] and eclk are slc interface signals (opt) ed[15:0] main control for start-up and power-down cs[0] cs_f vdd-bb to vdd-bb reg circuits jtdo } * 1 nf capacitor was recommended in previous designs, but use of this capacitor is now optional. rf filter rfa rfin (2) (2) (2) (2) vcc_io_ext nc (1) * notes: (1) vcc-io-ext is a no-connect pi n. internal power connections are made and no inte rnal wirebonds connect to pb. this is to enh ance the chip esd performance. (2) denotes a very small, short low c test point is desirable. s ample c onfiguration c onnection d iagram f or gsc3 f /lp x www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 10 b all c onfiguration figure 5. GSC3E/lpx and gsc3f/lpx 140 pin bga ball configuration diagram 1 2 3 4 5 6 7 8 9 10 a gnd_bb gpio1 cs_f gpio[0] rxa txa eclk sclk *ea[0] vddpll_o b rfpwrup mwe vdd_flash vdd_rtc eit[0] *ea[4] txb reserved *ea[1] vddk c gpio[14] ed[1] *ed[10] vdd_reg vdd_pll timemark rxb reserved *ea[3] vddk dmoe *ed[4] cs[0] vdd_bb gnd_bb gnd_bb *ea[2] *ea[5] *ea[6] tmode e gpio[15] *ed[9] *ed[8] vdd_bb gnd_bb gnd_bb wakeup *ea[7] *ea[8] rout f gpio[13] ed[3] ed[2] vdd_bb gnd_bb gnd_bb vdd_reg *ea[18] *ea[19] rin g ed[0] *ed[12] *ed[11] *ed[14] *ea[16] *ea[15] *ea[13] *ea[11] *ea[9] on_off hss [1] *ed[5] *ed[13] *ed[6] *ea[17] pll_filter *ea[14] *ea[12] *ea[10] reset j jtdi ed[7] *ed[15] clkacq_i sign_mag_i si sk so ss[ 0] sreset kjtrst vdd_bb agcpwm clkacq_o sign_mag _o spi_do spi_clk spi_di spi_ceb rtc_out l jtms vdd_bb vdd_bb gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf rtc_xo m jtdo vcc_rf vcc_rf vcc_rf vcc_rf vcc_rf vcc_rf vcc_rf vcc_rf vcc_rf n jtck gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf gnd_rf p grfrst xtal_in xtal_out tp_if gnd_rf rfin gnd_rf nc 3 vcc_rtc rtc_xi 1 2 3 4 5 6 7 8 9 10 notes 1. * = available for flash pre-loading for customers who use a special flash programmer with gsc3f/lpx compatible socket. 2. refer to table 1. for signals that have alternate functions. 3. in gsc3f-7879, this pin was vcc_io_ext. to meet the esd_hbm 2000v, it is internally connected to vcc_rf. no internal wirebon ds connect to this ball. www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 11 table 1. GSC3E(f)/lpx series pin identification name ball name ball name ball name ball agcpwm/gpio[2] k3 gnd_rf p5 ed[11] g3 ss [0] / gpio[3] j9 clkacq_i (in) j4 p7 ed[14] g4 ss [1]/ gpio[4] h1 clkacq_o (out) k4 gpio[0]/lna en a4 ea[16] g5 timemark / gpio[9] c6 cs [0] d3 gpio[1] / odo a2 ea[15] g6 tmode d10 gpio[13] / cts f1 gpio[14]/ rts c1 ea[13] g7 tp_if p4 cs_f a3 gpio[15]/yclk e1 ea[11] g8 txa a6 eclk a7 grfrst p1 ea[9] g9 txb b7 ed[0] g1 jtck n1 ed[5] h2 nc p8 ed[1] c2 jtdi j1 ed[13] h3 vcc_rf m3 ed[2] f3 jtdo m1 ed[6] h4 m4 ed[3] f2 jtms l1 ea[17] h5 m5 ed[7] j2 jtrst k1 ea[14] h7 m6 eit[0] / gpio[10] b5 moe d1 ea[12] h8 m7 gnd_bb a1 mwe b2 ea[10] h9 m8 d5 on_off g10 ed[15] j3 m9 d6 pll_filter h6 reset h10 m10 e5 ea[0] a9 rfin p6 vcc_rf m2 e6 ea[4] b6 rfpwrup b1 vcc_rtc p9 f5 reserved b8 rin f10 vdd_bb d4 f6 ea[1] b9 rtc_out k10 e4 gnd_rf l4 ed[10] c3 rtc_xi p10 f4 l5 reserved c8 rtc_xo l10 k2 l6 ea[3] c9 rxa a5 l2 l7 ed[4] d2 rxb c7 l3 l8 ea[2] d7 sclk a8 vdd_flash b3 l9 ea[5] d8 si j6 vdd_pll c5 n2 ea[6] d9 sign_mag_i (in) j5 vdd_reg c4 n3 ed[9] e2 sign_mag_o (out) k5 f7 n4 ed[8] e3 sk j7 vdd_rtc b4 n5 ea[7] e8 so j8 vddk b10 n6 ea[8] e9 spi_ceb k9 c10 n7 reserved e10 spi_clk k7 vddpll_o a10 n8 ea[18] f8 spi_di k8 wakeup e7 n9 ea[19] f9 spi_do k6 xtal_in p2 n10 ed[12] g2 sreset j10 xtal_out p3 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 12 table 2. GSC3E(f)/lpx signal description signals type description address and data pins - cpu interface cs [0] 1, 3 o flash memory chip select. cs_f 1 in internal flash chip select eclk 2 in external cmos clock source. ea[19:0] o external address bus. ed[15:0] i/o external data bus. ed[3:0] are used for strap options. ed[0] 4 i/o read on power-up to determine start address: 1 = internal rom (for reflash) 0 = external flash ed[1] 4 i/o must be pulled high. ed[3:2] 4 i/o read on power-up to determine boot clock: boot clock ed[3] ed[2] clkacq 0 0 clkacq 1 1 ed[6:4] 4 i/o external bus data bits 4 to 6. ed[7] 4 i/o must be pulled low. ed[15:8] 1, 4 o upper 8 bits of the bi-directional system data but. mwe , moe 3 o external memory write enable and output enable. sclk o test point. sreset in input to fsm. the system reset that triggers an internally generated reset called reset. the rtc counters are not affected by sreset . should be used only upon initial power-up of the device. not for use to enter or exit hibernate mode. debug interface pins jtdi, jtck, jtrst , jtms in jtag interface. during boot-strap these pins determine rf reference frequency as follows: frequency jtck jtdi 16.369 mhz 0 0 24.5535 mhz 0 1 26.0 mhz 1 0 reserved* 1 1 strapping options cannot be used when in debug mode, software must configure ref freq setting. *can also be programmed for 13, 16.8, or 19.2 mhz. see sirf representative for details. jtdo o part of jtag interface. gpio lines 6 gpio[0] 2, 4 i/o gpio lna enable gpio[1] 2, 4 i/o gpio line. alternate function is odometer interface for sirfdrive. gpio[2] 2 i/o gpio line. alternate function is agcpwm. gpio[4] i/o gpio line.default state is input mode. pad has no pull-up or pull-down resistor. gpio[9] 2,4 i/o gpio line (alt = timemark) gpio[10] 4 i/o gpio line. alternate function is eit[0]. pad has no pull-up or pull-down resistor. gpio[13] 4 i/o gpio line.used for sirfloc aided gps. alternate function is cs1 or cts. gpio[14] 1, 4 i/o gpio line. alternate function is cs2 or rts. gpio[15] 1, 4 i/o gpio line. alternate function is cs3 or yclk. GSC3E(f)/lpx rf signals clkacq_o o clkacq output. gnd_rf ground grfrst in rf reset input signal from fsm. rfin in rfa input; gps rf signal input. must be ac coupled. rtc_xi in rtc crystal oscillator i nput; a crystal network may be placed between this output and the rtc_xo input in lieu of using an external rtc oscillator. rtc_xo o rtc crystal oscillator output; a crystal network may be placed between this output and the rtc_xi input in lieu of using an external rtc oscillator. rtc_out o rtc crystal oscillator buffered output. spi_ceb , spi_di, spi_clk in rf synchronous serial interface (enable, data, and clock). reserved for rf to digital interface. spi_do o rf spi interface output. sign_mag_o o sign and mag combined output. tp_if o if test point. vcc_rf supply rf supply; must be properly bypassed. vcc_rtc supply rtc oscillator supply; must be properly bypassed. xtal_in in reference oscillator input. xtal_out output reference clock output. peripheral interface cts 1, 5 i/o clear to send/not, hardware flow control. alternate function is gpio[13]. eit[0] 4 i/o external interrupt[0]. alte rnate function is gpio[10]. on_off in edge triggered soft on or off request input to fsm. message mid205 or on_off pulse must be used to enter hibernate mode. on_off pulse must be used to wake up from hibernate mode. pll_filter ana external filter for pll (analog pin). rts / cs [2] 1, 5 i/o request to send/not, hardware flow control. alternate functions are cs2 and gpio[14]. rxa, rxb 1,6 in cmos-level serial receive ports for channel a and b. si, so, sk 2,4,5 i/o digital synchronous serial interface (in, out and clock). reserved for rf interface. ss [0] 1, 5 i/o spi slave select 0. timemark 2,4,5 i/o reserved. alternate function gpio[9]. tmode in reserved, tie low. txa, txb o cmos-level serial message output ports for channel a and b. yclk 1,4,5 in alt. functions: cs3 and gpio[15]. table 2. GSC3E(f)/lpx signal description (continued) signals type description www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 13 notes 1. internal pull-up resistor (30k nominal). 2. internal pull-down resistor (30k nominal). 3. default output high at reset. 4. default input at reset. 5. share function with gpio line. 6. gpio lines are 3.3 v tolerant. 7. all gnd and vcc pins must be connected to ensure reliable operation. good rf design practices must be adhered to in the pc board layout. a ground plane and a power plane must be used to obtain good performance. rf interface pins clkacq_i in data acquisition clock. reset od an fsm-generated rf chip reset based on sreset . this reset acts on the digital core, rf section, and any external devices controlled by reset . rfpwrup 3, 5 o power control for rf chip ldo. sign_mag_i in sign and magnitude bits. rtc interface pins rin in 32 khz clock input from rf section. rout o no connect. may be used as a test point. wakeup od wake-up power control for baseband ldo from fsm (open drain). 3.6 v max. all supplies gnd_bb (7) ground GSC3E(f)/lpx digital gnd. vdd_bb (6) supply digital section and i/o supply. vdd_flash supply flash power at 3 v (on gsc3f/lpx only). vddk supply core power at 1.2 v (if using vdd_reg, vddk requires output bypass capacitor). vddpll_o supply regulator output supply to pll. vdd_pll_in supply input power for pll. vdd_reg_in supply power input to core regulator (3 v). vdd_rtc supply rtc/bbram/fsm circuit supply (1.2v). table 2. GSC3E(f)/lpx signal description (continued) signals type description www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 14 electrical and power section e lectrical s pecifications note: maximum recommended differential between vdd_bb and vcc_rf is 0.3 v. * all rtc io/fsm are 3.3 v tolerant, exc ept for osc pad, which is 1.65 v tolerant. notes 1. peak acquisition current is characterized by millisecond burs ts above average acquisition current. 2. avg acq. current is typically only the first two seconds of ttff. 3. tracking current typically includes tracking and the post-acquisition portion of ttff. 4. during standby state: rtc block and co re remain powered on but clock is off. 5. rtc must always be powered during chip operation. notes 1. GSC3E(f)/lpx includes a hibernate st ate from which it can restart itself. 2. all external i/o lines must be driven low or disabled du ring battery back-up or hibernate state. warning ? stressing the device beyond th e ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions ? is not recommended and extended exposure beyond the ?operating conditio ns? may affect device reliability. table 3. absolute maximum ratings parameter symbol rating units digital core and i/o (volatile) power supply voltage vdd_bb 3.15 v input pin voltage vin 5.25 v output pin voltage vout 5.25 v latch-up current (includes internal flash die) ilatch 200 ma storage temperature tstg -65 to 150 c battery block (non-volatile) (rtc/bbram/fsm) power supply voltage vcc_rtc and vdd_rtc 2.0 v input pin voltage vrin 2.0 v output voltage vrout 2.0 v open drain pull-up voltage vod 3.8 v rf section maximum supply voltage vcc_rf 3.15 v maximum dc input (rfa) 10 dbm minimum dc voltage on any pin gnd -0.5 v maximum dc voltage on any pin 3.15 v rtc voltage* vcc_rtc 1.5 v this data sheet contains information about sirf products in their developm ent and sampling phases. sirf reserves the right to make changes in its products, specifications and other information at any time without notice. sirf assumes no liability or responsibility for any claims or damages arising out of the use of this data sheet, or from the use of integrated circuits base d on this data sheet, including, but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights. sirf makes no warranties, either express or implied with respect to the information and specific ations contained in this data sheet. performance char acteristics listed in this data sheet do not constitu te a warranty or guarantee of product performance. al l terms and conditions of sale are governed by the sirf terms and conditions of sale, a copy of which you may obtain from your authorized sirf sa les representative. table 4. operating conditions parameter symbol min. typ. max. units power supply voltage vdd_(all) 2.7 2.85 3.0 v power supply voltage vcc_(all) 2.7 2.85 3.0 v rtc/bbram/fsm supply voltage vcc_rtc and vdd_rtc 1.1 1.2 1.3 v operating temperature topr -40 85 c peak acquisition current 1 + internal flash idd 26 2.8 ma avg acquisition current 2 + internal flash idd 23 1.3 ma tracking current 3 + internal flash idd 22 1.0 ma standby current 4 idd 1.5 ma external reference amplitude (when driven externally, xtalin must be ac-coupled) 200 - 1200 mvpp ext. ref. frequency range 13 - 26 mhz rf front end gain 14 26 db table 5. battery conditions parameter symbol min. typ. max. units rtc supply vcc_rtc and vdd_rtc 1.1 1.2 1.3 v supply current 1, 2 iddrtc 10 a power supply 2 vdd 0 0 0 v www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 15 dc c haracteristics table 6. dc electrical characteristics for rtc block (non-volatile digital section) (pins: rin, rout, wakeup , on_off, sreset , reset , and tmode) parameter symbol min. typ. max. conditions units high level input voltage v ih 0.7 *v ddrtc v ddrtc +0.3 v low level input voltage v il -0.3 0.3*v ddrtc v switching threshold v t 0.5*v ddrtc v high level input current i ih -10 10 60 v in = v dd with pull-down a low level input current i il -10 10 -60 v in = v ss with pull-up a high level output voltage v oh v ddrtc -0.2 i oh = 100 a v low level output voltage v ol 0.2 i ol = 100 av input capacitance c in 5 input or bi-directional pf output capacitance c out 5 output buffer pf output current i oh and i ol 2none ma output current (rout only) i oh and i ol 1none ma table 7. dc electrical characteristics (volatile digital section) parameter symbol min. typ. max. conditions units high level input voltage v ih 0.7*v dd v dd +0.3 v low level input voltage v il -0.3 0.3*v dd v switching threshold v t 0.5*v dd v high level input current i ih -10 10 60 v in = v dd with pull-down a low level input current i il -10 10 -60 v in = v ss with pull-up a high level output voltage v oh *v dd -0.2 i oh =100 av low level output voltage v ol 0.2 i ol = 100 a v tri-state output leakage i oz -10 10 v out = v ss or v dd a input capacitance c in 5 input or bi-directional pf output capacitance c out 5 output buffer pf output current (memory bus) i oh and i ol 4none ma output current (gpio and others) i oh and i ol 2none ma www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 16 table 8. GSC3E(f)/lpx dc electrical characteristics (rf section) all specifications under c onditions t=25c, vcc=2.85 v. parameter symbol min. typ. max. units conditions total supply current spi mode sleep (rf domain) normal power clock only mode i cc - - - 0.006 13 1 0.009 15 ma full power acq clk and rtc only spi cmos input high level v ih vcc_rf * 0.8 -- v spi cmos input low level v il - - vcc_rf * 0.2 v www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 17 ac c haracteristics (GSC3E/lpx) figure 6. write access timing diagram table 9. ac characteristics for write access parameter list timing min. 2 max. 2 unit cs mwe t1 5.6 9 ns ea mwe t2 10 12 mwe pulse width 1 t3 59.1 60 mwe cs t4 11.7 18.1 mwe ea t5 29.5 30.4 1. with two wait states; width = 20.13 + (#ws x 20*) * cpu clock periods 2. min and max values are from best and worst operating conditions all measurements in table 9 and tabl e 10 are characterized except as not ed with (*) which are guaranteed by design. 4 4 4 4 4 -7% #3 %$ %! www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 18 1. with two wait states; width = 20.13 + (#ws x 20*) * cpu clock periods 2. min and max values are from best and worst operating conditions figure 7. read access timing diagram table 10. ac characteristics fo r read access (GSC3E/lpx) parameter list timing min. 2 max. 2 unit cs moe t1 5.9 8.9 ns ea moe t2 10.1 11.4 ed moe t3 15.4 18 moe pulse width 1 t4 60 60.6 moe cs t5 11.5 17 moe ea t6 48.7 50.1 t5 t4 t6 t2 t1 moe cs ed ea t3 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 19 figure 8. power sequencing diagram battery insertion sequence power down sequence power up sequence bb/rf reg input bb/rf reg output nwakeup rtc reg input nsreset on_off (or mid205) tx/rx (i/o leakage on_off pulse on_off pulse or mid205 see note 1 note 1: if bb/rf reg input voltage is removed, optional reset circuitry is required. full power operation 100 ms min tale 11. sc3e(f)/lpx thermal characteristics parameter symbol typical units conditions thermal resistance junction-to-ambient 40 c/w ja d www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 20 table 12. GSC3E(f)/lpx rf section ac characteristics all specifications under conditions t=25 c, vcc=2.85 v . all rf measurements are made with appropriat e matching to the input or output impedance. ac characteristic symbol min. typical max. units conditions rfa/mixer/agc noise figure (agc @ min. gain) nf - 6.0 11 db input 1 db gain compression (agc @ min. gain) ip 1db --65-dbm input return loss w/ external match (fig 10) rl - 9.5 - db image rejection ratio (agc @ min. gain) 20 - - db if filter/agc-amp filter attenuation at 12 mhz f(12 mhz) 20 - - db filter bandwidth bw - 7 - mhz 3 db bandwidth voltage gain resolution - 1.7 - db gain adjust range 45 51 - db minimum receiver gain - 50 - db maximum receiver gain - 100 - db gain linearity -2.0 - 2.0 db frequency synthesizer operating frequency 1571.424 mhz type of synthesizer integer-n reference frequency 13 - 26 mhz 6 discrete frequencies reference input level 200 - 1200 mvpp 50% duty (1) cmos driver logic level high v oh v cc_io_ext * 0.9 -- v logic level low v ol --v cc_io_ext * 0.1 v rise time @ 12 pf load (10% to 90%) - 4.0 ns fall time @ 12 pf load (90% to 10%) - 4.0 ns static sink current and source current vcc 5 k -- ma (1) must meet performance standards defined in sirf tcxo ssiii per formance specification. www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 21 figure 9. typical tcxo circuitry figure 10. sample rfin input im pedance matching circuitry table 13. operating modes operating modes comments normal power entire chip enabled (normal operation). cpu only the rf section pll and receiver chain are disabled. all other circuits are powered. this mode is used during low power operations such as tricklepower or advanced power management. it allows the GSC3E(f) /lpx to save power by shutting down portions of the rf section while it is idle and the sirfstariii core and arm are still performing. standby the rf section is disabled. the digi tal section clocks are idle. the rtc and battery back up sections are powered. this mode allows the GSC3E(f)/lpx to minimize power consumption while the chip is in brief idle period such as during a power management cycle. hibernate all circuits except the rtc from on_off and battery-backed sram are disabl ed. can wake-up at a preset time or by exter nal interrupt vin from on_off. tcxo 0.01 f vc xtalin xtalout c x 1 nf 3 pf 3.9 nh rfin 22 pf www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 22 i nput i mpedance s mith c harts figure 11. narrowband input impeda nce smith chart for GSC3E(f)/lpx table 14. rfa input impedance over frequency (s11) test conditions: rf input = -60 dbm, zo = 50 , 2.85 v, 25 c. no matching circuitry was used for these measurements. marker 1 2 3 frequency 1,475 mhz 1,575 mhz 1,675 mhz impedance 6.7 - j 20.6 9.9 - j 15.4 16.4 - j 15.0 -25 -10 0 25 10 10 25 50 500 200 100 3 2 1 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 23 figure 12. wideband input impedance smith chart for GSC3E(f)/lpx table 15. rfa input impedance over frequency (s11) test conditions: rf input = -60 dbm, zo = 50 , 2.85 v, 25 c. no matching circuitry was used for these measurements. marker 1 2 3 frequency 1,000 mhz 1,575 mhz 2,000 mhz impedance 5.489 - j 44.76 9.572- j 15.38 8.66- j 15.36 -25 -10 0 25 10 10 25 50 500 200 100 3 2 1 www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 24 mechanical section m echanical s pecifications - p ackaging d iagram figure 13. GSC3E(f)/lpx 140 pin bga package www.datasheet.in
GSC3E/lpx and gsc3f/lpx: high performa nce, lowest power, gps single chip preliminary datasheet s sirf proprietary and confidential s 1055-1061 may 2009 s www.sirf.com page 25 a dditional i nformation o rdering i nformation sirf has evaluation kits available for this product to allow you to conduct various performance tests. sirf also supports developers through the availability of a system developer kit which includes access to application notes and reference designs; and support from sirf engineers for design, testing, troublesh ooting, and prototype evalu- ation. sirf gsw firmware may also be modified thro ugh a sirf firmware developer kit which allows limited modification and configuration of sirf standard firmware, as well as incorporat ion of a small amount of user code. additional arm development tools must be purchased separately. part number description GSC3E/lpx-7985 GSC3E/lpx, 16-bit, 140-pin, bga, lead-free gsc3f/lpx-7989 gsc3f/lpx, 16-bit, 140-pin, bga, lead-free development tools 9900-0286 GSC3E(f)/lpx evaluation kit 9900-0293 GSC3E(f)/lpx system development kit (sdk) worldwide sales offices no r th ame r ica corporate hq (1) (408) 467-0410 sales@sirf.com eu r ope united kingdom (44) (1344) 668390 salesuk@sirf.com germany (49) (81) 529932-90 salesgermany@sirf.com asia paci?c china (86) (21) 5854-7127 saleschina@sirf.com taiwan (886) (2) 8174-8966 salestaiwan@sirf.com japan (81) (44) 829-2186 salesjapan@sirf.com india (91) (80) 41966000 salesindia@sirf.com south korea (82) (2) 545-2562 saleskorea@sirf.com 2009 si technoloy inc. a memer of he cs plc rop of companies. this docmen conains proprieary and conf idenial informaion reardin si prodcs and is proided only nder a non-disclo sre areemen. si reseres he rih o mae chanes o is prodcs and spec ificaions a any ime and wiho noice. si maes no warran y eiher epress or implied as o he accracy of he informaion in his docm en. erformance characerisics lised in his docmen do no con sie a warrany or aranee of prodc performance. ll erms and condiions of sale are oerned y separae erms and condiions a copy of whi ch may e oained from yor ahoried si sales represenai e. si sisar and si wih he ori desin in prple and old are reisered rademars of si technoloy inc. the si prodcs descried in his docmen are proeced y one or more pa ens raned in he unied saes and worldwide. o saemens or represena ions in his docmen are o e consred as aderisin marein or offerin for sale in he un ied saes impored prodcs sec o he cease and esis rder issed y he u. s. inernaional trade commission in is inesiaion o. 337-t -602. sch prodcs inclde sisar iii chips that operate with sirf software that supports sirfinstantfix and/or sirfloc servers, or contains syncfreenav functionality. no statements or representat ions in this document are to be construed as advertising, marketing, or offering for sale in the un ited states imported covered products subject to the cease and desist order issued by the u.s. international trade commission in its investigation n o. 337-ta-602. such products include sirfstariii chips that oper ate with sirf software that supports sirf instantfix, and/or sirfloc servers, or con tains syncfreenav functionality. www.datasheet.in

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